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ADM1191
WRITE EXTENDED COMMAND BYTE
Data Sheet
In the write extended command byte operation, the master
device writes to one of the three extended registers of the slave
device, as follows:
7.
8.
The slave asserts an acknowledge on SDA.
The master asserts a stop condition on SDA to end the
transaction.
1.
The master device asserts a start condition on SDA.
1
2
3
4
5
6
7 8
REGISTER
SLAVE
2.
3.
4.
The master sends the 7-bit slave address, followed by the
write bit (low).
The addressed slave device asserts an acknowledge on SDA.
The master sends the register address byte. The MSB of
this byte is set to 1 to indicate an extended register write.
The two LSBs indicate which of the three extended registers is
EXTENDED
S ADDRESS W A ADDRESS A COMMAND A P
BYTE
Figure 21. Write Extended Byte
Table 9, Table 10, and Table 11 provide the details of each
extended register.
5.
6.
to be written to (see Table 8). All other bits should be set to 0.
The slave asserts an acknowledge on SDA.
The master sends the extended command byte (refer to
Table 9, Table 10, and Table 11).
Table 8. Extended Register Addresses
A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 1
0 0 0 0 0 1 0
Extended Register
ALERT_EN
ALERT_TH
0
0
0
0
0
1
1
CONTROL
Table 9. ALERT_EN Register Operations
Bit
0
1
Default
0
0
Name
EN_ADC_OC1
EN_ADC_OC4
Function
LSB, enabled if a single ADC conversion on the I channel exceeds the threshold set in the ALERT_TH register.
Enabled if four consecutive ADC conversions on the I channel exceed the threshold set in the
ALERT_TH register.
2
0
EN_OC_ALERT
Enables the OC_ALERT register. If an overcurrent condition is present compared to the SETV threshold,
the OC_ALERT register captures and latches this condition.
3
4
0
0
EN_OFF_ALERT
CLEAR
Set this bit high to activate the SWOFF bit (see Table 11).
Clears the OFF_ALERT, OC_ALERT, and ADC_ALERT status bits in the status register. The value of these bits
may immediately change if the source of the alert is not been cleared and the alert function is not disabled.
The CLEAR bit self-clears to 0 after the STATUS register bits have been cleared.
Table 10. ALERT_TH Register Operations
Bit
7:0
Default
FF
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit value
corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
0
Default
0
Name
SWOFF
Function
LSB, forces the ALERTB pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. C | Page 12 of 16
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